Volantis Semiconductor, Inc. Jobs
Open positions at Volantis Semiconductor, Inc., newest first. Each listing links to the company's own application page.
- Open positions
- 23
Newest Volantis Semiconductor, Inc. openings
Hybrid Remote/SF Bay Area/Austin/Boston · 13 days ago
Advanced Packaging Engineer
$250k – $400k/yrHybrid Remote/SF Bay Area/Austin/Boston · 30 days ago
You will contribute to and own aspects of the Volantis A-0 and A-1 package.
- Mid-level
- advanced semiconductor packaging
- package design
- thermomechanical analysis
Hybrid Remote/SF Bay Area/Austin/Boston · 30 days ago
We're seeking experienced engineers to contribute to flip chip package development and assembly processes for advanced semiconductor devices (2.5D/3D/chiplet/fan-out/flip-chip).
- Full-time
- Mid-level
- flip chip packaging
- bump metallurgy
- underfill processes
DFT Lead
HybridHybrid Remote/SF Bay Area/Austin/Boston · 30 days ago
We're looking for DFT engineers to contribute to and own DFT efforts for blocks and entire dies on the A-0 and A-1 wafer-scale systems.
- Full-time
- Lead / Staff
- design for test (DFT)
- SoC tapeout
- advanced node design
PIC Design Engineer
HybridHybrid Remote/SF Bay Area/Austin/Boston · 30 days ago
We're looking for PIC (photonic integrated circuit) design engineers to contribute to and own aspects of the wafer-scale photonic interposer PIC. This will involve solving unique problems…
- Full-time
- Mid-level
- photonic integrated circuit design
- optical coupling
- PIC tapeout
Wafer Architect
HybridHybrid Remote/SF Bay Area/Austin/Boston · 30 days ago
We're looking for an architect to own the logical architecture for the A-0 and A-1 wafer products. You will work with the XPU/Compute chip architect and the memory architect to synthesize…
- Full-time
- Lead / Staff
- AI chip architecture
- memory sub-systems
- LLM inference workloads
Micro-Optics Engineer
HybridHybrid Remote/SF Bay Area/Austin/Boston · 30 days ago
We are seeking a Senior Micro-Optics/Microlens Array Engineer to design, model, and validate microlens-array and wafer-level micro-optical components for high-density photonic packages.
- Full-time
- Senior
- microlens array design
- Zemax OpticStudio
- tolerance analysis
Link Validation Engineer
HybridHybrid Remote/SF Bay Area/Austin/Boston · 30 days ago
We're looking for link validation engineers to help with DVT and bringup of the core optical link and PHY.
- Full-time
- Senior
- optical link bringup
- DVT
- PHY design
PHY/SERDES Lead
HybridHybrid Remote/SF Bay Area/Austin/Boston · 30 days ago
We're looking for a PHY/SERDES Lead to own and lead the development of our semi-custom optical PHY layer.
- Full-time
- Lead / Staff
- SERDES design
- PHY tapeout
- link architecture
XPU Architect
HybridHybrid Remote/SF Bay Area/Austin/Boston · 30 days ago
We're looking for an XPU Architect to own the XPU compute engine architecture of the A-0 and A-1 systems. This will initially involve heavily leveraging existing 3rd party IP, but in a…
- Full-time
- Director
- computer architecture
- silicon implementation
- AI workload performance analysis
Hybrid Remote/SF Bay Area/Austin/Boston · 30 days ago
We're looking for mechanical design engineers to contribute to, and own aspects of the wafer-scale assembly, including the interactions between the power delivery system, mechanical…
- Full-time
- Mid-level
- mechanical design
- multi-material assembly
- thermal management
Hybrid Remote/SF Bay Area/Austin/Boston · 30 days ago
- Full-time
- Mid-level
- integrated photonics packaging
- multi-die assembly
- MCM assembly
ASIC Design Engineer
HybridHybrid Remote/SF Bay Area/Austin/Boston · 30 days ago
We're looking for ASIC design engineers to contribute to and own blocks in the development of the A-0 and A-1 wafer products, across both the XPU, memory chiplet and other dies on the wafer.
- Full-time
- Mid-level
- ASIC design
- advanced node tapeouts
- PPA optimization
SoC Architect
HybridHybrid Remote/SF Bay Area/Austin/Boston · 30 days ago
We're looking for SoC architects to own the detailed SoC-level architecture of dies on the A-0 and A-1 wafer-scale systems. You will work with the architecture and ASIC design teams to…
- Full-time
- Director
- SoC architecture
- microarchitecture
- physical design
IO Module Engineer
HybridHybrid Remote/SF Bay Area/Austin/Boston · 30 days ago
We're looking for engineers to contribute to the thermomechanical, electrical and mechanical design and assembly of the IO modules that attach to our A-0 and A-1 wafers.
- Full-time
- Mid-level
- signal integrity signoff
- copper and electro-optic connector interfaces
- connectorized link bringup
Architect- Subsystem
HybridHybrid Remote/SF Bay Area/Austin/Boston · 30 days ago
We're looking for architects to own key blocks on the A-0 and A-1 systems. This is a role with ownership of an entire sub-block, and you will need to understand how it fits into the entire…
- Director
- AI accelerator design
- microarchitecture
- block-level architecture
Hybrid Remote/SF Bay Area/Austin/Boston · 30 days ago
We're looking for a hands-on process and materials engineer to own wafer level molding and underfill processes, material qualification, and assembly integration across development and…
- Full-time
- Mid-level
- wafer level molding
- underfill process development
- thermo-mechanical reliability
PCB Design Engineer
HybridHybrid Remote/SF Bay Area/Austin/Boston · 30 days ago
We're looking for PCB design engineers to design and own various PCB boards that are components in the A-0 and A-1 system assemblies.
- Full-time
- Mid-level
- PCB design
- high-density interconnect
- design for manufacturing
Hybrid Remote/SF Bay Area/Austin/Boston · 30 days ago
We're seeking an experienced engineer to lead bump interconnect development for advanced semiconductor devices (2.5D/3D/chiplet/fan-out).
- Full-time
- Mid-level
- bump interconnect processes
- RDL plating
- failure analysis
Hybrid Remote/SF Bay Area/Austin/Boston · 30 days ago
We're looking for power integrity engineers to ensure that power is delivered and stable at all levels: rack/tray, package, die, core.
- Senior
- PDN analysis and design
- advanced node (7nm and lower)
- large die high TDP chip power integrity
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