OpenAI
AI & Machine LearningDirect Ashby career site

Design Verification Engineer

Location
San Francisco, CA (Remote) · On-site
Job type
Full-time
Level
Mid-level
Experience
3+ years
Education
Bachelor's degree
Listed
30 days ago

Skills & highlights for this role

  • SystemVerilog
  • UVM
  • hardware verification
  • computer architecture
  • constrained-random testbenches

Also useful

  • VCS
  • Questa
  • Verdi
  • formal verification
  • emulation

About the Role

OpenAI is developing custom silicon to power the next generation of frontier AI models. We’re looking for experienced Design Verification (DV) Engineers to ensure functional correctness and robust design for our cutting-edge ML accelerators. You will play a key role in verifying complex hardware systems-ranging from individual IP blocks to subsystems and full SoC-working closely with architecture, RTL, software, and systems teams to deliver reliable silicon at scale.

In this role you will

  • Own the verification of one or more of: custom IP blocks, subsystems (compute, interconnect, memory, etc.), or full-chip SoC-level functionality.
  • Define verification plans based on architecture and microarchitecture specs.
  • Develop constrained-random, directed, and system-level testbenches using SystemVerilog/UVM or equivalent methodologies.
  • Build and maintain stimulus generators, checkers, monitors, and scoreboards to ensure high coverage and correctness.
  • Drive bug triage, root cause analysis, and work closely with design teams on resolution.
  • Contribute to regression infrastructure, coverage analysis, and closure for both block- and top-level environments.

You might thrive in this role if you have

  • BS/MS in EE/CE/CS or equivalent with 3+ years of experience in hardware verification.
  • Proven success verifying complex IP or SoC designs in industry-standard flows
  • Proficient in SystemVerilog, UVM, and common simulation and debug tools (e.g., VCS, Questa, Verdi).
  • Strong knowledge of computer architecture concepts, memory and cache systems, coherency, interconnects, and/or ML compute primitives.
  • Familiarity with performance modeling, formal verification, or emulation is a plus.
  • Experience working in fast-paced, cross-disciplinary teams with a passion for building reliable hardware.

Additional information

To comply with U.S. export control laws and regulations, candidates for this role may need to meet certain legal status requirements as provided in those laws and regulations.

About the Team

OpenAI’s Hardware organization develops AI-native silicon and system-level solutions for the unique demands of advanced AI workloads. Building on efforts like Jalapeño, the team is developing future generations of AI-native silicon and tightly integrated systems to power the next generation of frontier models. By co-designing chips, systems, tools, and methodologies, the team helps deliver faster, more efficient, and production-ready hardware for OpenAI’s supercomputing platform.

About OpenAI

OpenAI is an AI research and deployment company dedicated to ensuring that general-purpose artificial intelligence benefits all of humanity. We push the boundaries of the capabilities of AI systems and seek to safely deploy them to the world through our products. AI is an extremely powerful tool that must be created with safety and human needs at its core, and to achieve our mission, we must encompass and value the many different perspectives, voices, and experiences that form the full spectrum of humanity.

To notify OpenAI that you believe this job posting is non-compliant, please submit a report through this form No response will be provided to inquiries unrelated to job posting compliance.

Read the original posting

From OpenAI's careers page, first listed on Rolev.ai on October 10, 2026. Rolev.ai is not the employer.

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Common questions

Where is the Design Verification Engineer job at OpenAI located?

Yes, this Design Verification Engineer opening at OpenAI is listed as San Francisco, CA (Remote) (On-site). Always check OpenAI's application page for specific state eligibility or relocation policies.

What qualifications are required for Design Verification Engineer at OpenAI?

For the Design Verification Engineer role, OpenAI highlights 3+ years of relevant experience; a bachelor's degree; experience with SystemVerilog, UVM, hardware verification, computer architecture, constrained-random testbenches. Rolev.ai can score your existing resume against these requirements and show any skill gaps before you apply.

How do I apply for the Design Verification Engineer position at OpenAI?

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