Design Verification Engineer

About the role

Why join Upscale, Inc.

Upscale, Inc., is building the high-performance infrastructure powering the next generation of artificial intelligence. Backed by over $300M in funding and rapid global adoption, we are scaling systems designed for the world’s most demanding AI workloads.

We focus on first-principles engineering across silicon, systems, and networking-where performance, scale, and execution are critical. Our team is talent-dense and high-performing. We value ownership, technical rigor, and speed, and we offer the opportunity to work on foundational problems with immediate, real-world impact.

If you’re looking to do high-impact work, move fast, and help define the infrastructure behind the future of AI-Upscale is where you can produce meaningful work at the frontier-and operate at a high standard.

Job Responsibilities

• Design, develop, and maintain robust verification environments, testbenches, reusable verification components, and reference models for block- and system-level designs.
• Develop comprehensive verification plans and create test cases to ensure complete functional coverage.
• Verify RTL designs at both block and chip levels using directed testing, constrained-random verification, assertion-based verification (ABV), formal verification techniques, and functional coverage methodologies.
• Perform RTL code coverage analysis, assertion coverage, functional coverage, and gate-level simulations to validate design quality and completeness.
• Debug and resolve design and verification issues by collaborating closely with design, architecture, and cross-functional engineering teams.
• Drive the adoption of advanced verification methodologies, automation frameworks, and best practices to improve verification quality and efficiency.
• Apply data-driven analytics and AI-assisted techniques to improve test generation, regression analysis, coverage optimization, and debug productivity.
• Continuously improve verification processes, infrastructure, and reusable verification IP to accelerate development cycles and enhance design quality and reliability.