Front-End Power Engineer

Key responsibilities

• Optimize RTL designs to boost power efficiency while meeting performance and area objectives.
• Perform power analysis throughout various stages of silicon design, applying power-saving strategies in RTL such as clock gating, power gating, multi-voltage domains, and dynamic voltage scaling.
• Conduct power estimation and evaluate PPA trade-offs for both new and existing design features.
• Collaborate closely with the physical design team to ensure power targets are met during the synthesis, place-and-route (P&R), and sign-off phases.
• Create precise power models from RTL simulations and gate-level netlists, and perform power roll-up analysis to estimate chip-level power consumption under different conditions.

You may be a good fit if you have

• Experience in RTL development using Verilog/SystemVerilog, with a focus on low-power RTL design and optimization for complex digital systems.
• In-depth knowledge and experience in implementing low-power techniques like clock gating, power gating, and dynamic voltage/frequency scaling (DVFS).
• Familiarity with synthesis and place-and-route processes with an emphasis on optimizing for power.

Strong candidates may also have experience with

• UPF/CPF power intent specifications.
• Power analysis tools such as Synopsys PrimePower, Cadence Joules, or similar.
• Automation of power analysis and optimization workflows using scripting languages (Tcl, Perl, Python).

Benefits

• Full medical, dental, and vision packages, with 100% of premium covered
• Housing subsidy of $2,000/month for those living within walking distance of the office
• Daily lunch and dinner in our office
• Relocation support for those moving to Cupertino

How we're different

Etched believes in the Bitter Lesson. We think most of the progress in the AI field has come from using more FLOPs to train and run models, and the best way to get more FLOPs is to build model-specific hardware. Larger and larger training runs encourage companies to consolidate around fewer model architectures, which creates a market for single-model ASICs.

We are a fully in-person team in Cupertino, and greatly value engineering skills. We do not have boundaries between engineering and research, and we expect all of our technical staff to contribute to both as needed.