Power Optimization Engineer

Key responsibilities

• Develop chip power model from chip architecture, estimate chip power from microarchitecture, and devise power saving techniques for product use cases.
• Work closely with Architects, Performance Engineers, Software Engineers, ASIC Design Engineers, and Physical Design teams to implement design for optimal power using advanced power management techniques.
• Estiate and analyze power consumption data at both full-chip and unit levels, guiding ASIC teams to enhance the power efficiency of all functional units both pre-silicon and post silicon. Correlate the estimated power consumption to the measured power.

You may be a good fit if you have

• Experience in power optimization using dynamic voltage and frequency scaling techniques, power aware synthesis, glitch power reduction techniques as well as efficient power delivery network implementation.
• Experience with gate-level power optimization through VCD-based and/or FSDB-based power analysis.
• Strong understanding of concepts of energy consumption, estimation, data movement, low power design, and power-saving features.

Strong candidates may also have experience with

• Digital design and optimization using industry-standard power analysis tools and methodologies.
• Leading power optimization at RTL and layout level using PrimePower, VCD-based analysis, DVFS, clock power reduction, clock gating, and glitch reduction techniques.

Benefits

• Full medical, dental, and vision packages, with 100% of premium covered
• Housing subsidy of $2,000/month for those living within walking distance of the office
• Daily lunch and dinner in our office
• Relocation support for those moving to Cupertino

How we're different

Etched believes in the Bitter Lesson. We think most of the progress in the AI field has come from using more FLOPs to train and run models, and the best way to get more FLOPs is to build model-specific hardware. Larger and larger training runs encourage companies to consolidate around fewer model architectures, which creates a market for single-model ASICs.

We are a fully in-person team in Cupertino, and greatly value engineering skills. We do not have boundaries between engineering and research, and we expect all of our technical staff to contribute to both as needed.