Low-Power Design Engineer
- Location
- Palo Alto, CA · On-site
- Job type
- Full-time
- Level
- Senior
- Experience
- 5+ years
- Listed
- 21 days ago
Skills & highlights for this role
- UPF power intent
- low-power verification
- CDC/RDC analysis
- power-aware simulation
- Python or Tcl scripting
Also useful
- VC LP
- Conformal Low Power
- PowerArtist
- SpyGlass
- formal verification of power intent
About this Role
You'll own power intent from architecture through signoff. You'll design and verify low-power architectures on real silicon programs with leading semiconductor companies while helping Voltai's AI learn power-aware design.
What You’ll Do
- Define power architecture and write UPF power intent for SoCs and IP.
- Implement and verify power gating, clock gating, multi-voltage domains, and retention.
- Run power-aware simulation, static low-power checks, and CDC/RDC analysis.
- Partner with RTL, physical design, and signoff teams on power estimation and closure.
- Build automation for power analysis and reporting.
- Evaluate AI-generated power intent and help define what correct looks like.
What We’re Looking For
- 5+ years of low-power design or verification experience on production tapeouts.
- Expert UPF knowledge and experience with power-aware verification.
- Hands-on experience with tools like VC LP, Conformal Low Power, or PowerArtist.
- Experience with CDC/RDC tools (SpyGlass, Questa CDC, or similar).
- Python or Tcl scripting.
Bonus Points
- Experience with mobile, edge, or data-center power management.
- Formal verification of power intent.
- Interest in AI-assisted design tools.
About Voltai
Voltai is developing world models, and agents to learn, evaluate, plan, experiment, and interact with the physical world. We are starting out with understanding and building hardware; electronics systems and semiconductors where AI can design and create beyond human cognitive limits.
About the Team
Backed by Silicon Valley’s top investors, Stanford University, and CEOs/Presidents of Google, AMD, Broadcom, Marvell, etc. We are a team of previous Stanford professors, SAIL researchers, Olympiad medalists (IPhO, IOI, etc.), the inventors of IC3 and the Murphi verification system, CTOs of Synopsys & GlobalFoundries, Head of Sales & CRO of Cadence, former US Secretary of Defense, National Security Advisor, and Senior Foreign-Policy Advisor to four US presidents.
From Voltai's careers page, first listed on Rolev.ai on October 19, 2026. Rolev.ai is not the employer.
How Rolev.ai helps with this application
Rolev.ai is a job search and application tool for US job seekers. For this Low-Power Design Engineer role at Voltai, it shows how your resume fits, tailors your resume to the posting, and prepares the application for you to review.
See how you fit
Openings from employer career sites are ranked against your whole resume—and searchable inside Claude, ChatGPT, and Cursor via Rolev.ai MCP.
Tailor without inventing
Every change to your resume is checked against your original. New experience goes in only with your yes—zero fabricated claims.
Draft the full kit
Tailored and Full Match resumes, role-specific cover letters, and answers to employer screening questions are prepared in seconds.
1-Click Extension Autofill
The Chrome extension fills the employer's Greenhouse, Workday, Lever, or Ashby form in 1 click. You review it and press Submit.
Similar roles
All Electronics Engineer jobs- Staff Systems EngineerNgc · Melbourne, FL · $153k – $229k/yr
- Etch Equipment EngineerNxp · Austin, TX
- Senior Staff Analog Design EngineerRenesas Electronics · Chandler, AZ
- Wireless Hardware Engineer Intern - Summer 2027Skydio · San Mateo, CA
- Silicon Photonics Control & Calibration Engineer - Optical Circuit Switches (OCS)Voyant Photonics · New York, NY
- Test EngineerNgc · Elkton, MD · $87.6k – $131k/yr
Common questions
Where is the Low-Power Design Engineer job at Voltai located?
This Low-Power Design Engineer position at Voltai is located in Palo Alto, CA (On-site). Always check Voltai's application page for specific state eligibility or relocation policies.
What qualifications are required for Low-Power Design Engineer at Voltai?
For the Low-Power Design Engineer role, Voltai highlights 5+ years of relevant experience; experience with UPF power intent, low-power verification, CDC/RDC analysis, power-aware simulation, Python or Tcl scripting. Rolev.ai can score your existing resume against these requirements and show any skill gaps before you apply.
How do I apply for the Low-Power Design Engineer position at Voltai?
This listing links directly to Voltai's Ashby application page. You can apply directly on Voltai's site, or use Rolev.ai to check your resume fit, generate a zero-hallucination tailored resume and cover letter for this posting, and autofill the Ashby application form in 1 click with the Rolev.ai Chrome extension. You always review the form and press Submit yourself.