RTL Design Engineer
- Location
- Palo Alto, CA · On-site
- Job type
- Full-time
- Level
- Senior
- Experience
- 5+ years
- Listed
- 21 days ago
Skills & highlights for this role
- RTL design
- SystemVerilog
- microarchitecture
Also useful
- SVA
- formal verification
- UPF low-power design
About this Role
You'll design and own RTL for production silicon, from microarchitecture to signoff-ready code. You'll work on real chip programs with leading semiconductor companies while helping Voltai's AI learn to write, review, and debug RTL the way the best designers do.
What You’ll Do
- Own microarchitecture and RTL implementation for IP blocks and subsystems in SystemVerilog.
- Drive designs through lint, CDC/RDC, synthesis, and timing closure with the backend team.
- Partner with verification and formal teams on test plans, assertions, and coverage closure.
- Debug complex functional and timing issues across simulation, emulation, and silicon.
- Review and evaluate AI-generated RTL, and help define what correct, high-quality design looks like.
- Work directly with customer design teams when needed.
What We’re Looking For
- 5+ years of RTL design experience on chips that taped out.
- Expert SystemVerilog/Verilog and strong microarchitecture skills.
- Hands-on experience with lint, CDC, synthesis, and timing-aware design.
- Familiarity with common protocols (AXI, PCIe, Ethernet, DDR, or similar).
- Python or Tcl scripting.
Bonus Points
- Experience writing SVA or working with formal verification.
- Low-power design (UPF, clock and power gating).
- Interest in AI-assisted design tools.
About Voltai
Voltai is developing world models, and agents to learn, evaluate, plan, experiment, and interact with the physical world. We are starting out with understanding and building hardware; electronics systems and semiconductors where AI can design and create beyond human cognitive limits.
About the Team
Backed by Silicon Valley’s top investors, Stanford University, and CEOs/Presidents of Google, AMD, Broadcom, Marvell, etc. We are a team of previous Stanford professors, SAIL researchers, Olympiad medalists (IPhO, IOI, etc.), the inventors of IC3 and the Murphi verification system, CTOs of Synopsys & GlobalFoundries, Head of Sales & CRO of Cadence, former US Secretary of Defense, National Security Advisor, and Senior Foreign-Policy Advisor to four US presidents.
From Voltai's careers page, first listed on Rolev.ai on October 19, 2026. Rolev.ai is not the employer.
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Common questions
Where is the RTL Design Engineer job at Voltai located?
This RTL Design Engineer position at Voltai is located in Palo Alto, CA (On-site). Always check Voltai's application page for specific state eligibility or relocation policies.
What qualifications are required for RTL Design Engineer at Voltai?
For the RTL Design Engineer role, Voltai highlights 5+ years of relevant experience; experience with RTL design, SystemVerilog, microarchitecture. Rolev.ai can score your existing resume against these requirements and show any skill gaps before you apply.
How do I apply for the RTL Design Engineer position at Voltai?
This listing links directly to Voltai's Ashby application page. You can apply directly on Voltai's site, or use Rolev.ai to check your resume fit, generate a zero-hallucination tailored resume and cover letter for this posting, and autofill the Ashby application form in 1 click with the Rolev.ai Chrome extension. You always review the form and press Submit yourself.