Silicon Operations Program Manager

Key Responsibilities

Production Planning & Scheduling

• Develop and maintain end-to-end production schedules for silicon wafers, interposers, and test/assembly, supporting phases from engineering builds to mass production.
• Coordinate with foundries, OSATs (Outsourced Semiconductor Assembly and Test providers), and internal stakeholders to ensure production milestones and quality goals are met.
• Collaborate with test engineering teams to coordinate ATE test program development, bring-up planning, and bench validation hardware readiness.
• Track and forecast capacity planning across all silicon manufacturing stages, including wafer fabrication, component procurement, assembly, and test.

Supply Chain Coordination

• Manage the procurement, delivery, and scheduling of key silicon components (e.g., wafers, interposers, substrates) to ensure optimal time-to-market.
• Act as the operational lead between internal teams and suppliers, ensuring transparency and alignment across silicon, packaging, validation, and manufacturing.
• Prepare for mass production ramp by ensuring material readiness, test infrastructure availability, and logistic support to mitigate bottlenecks or delays.

Forecasting & Reporting

• Build and maintain demand forecasts for silicon and related components, based on build plans, yield assumptions, validation schedules, and market dynamics.
• Share regular forecasts with supply chain partners and ensure proactive capacity allocation at foundries and OSATs.
• Generate and maintain detailed dashboards and reports to track schedule adherence, capacity utilization, inventory status, and delivery performance for executive and technical stakeholders.

You May Be a Good Fit If You Have

• Bachelor’s degree in Supply Chain Management, Industrial Engineering, Operations Management, or a related field.
• 5+ years of experience in supply chain management, production planning, or operations within the semiconductor industry.
• Deep understanding of the silicon lifecycle: tape-out, fabrication, packaging, test, bring-up, and validation
• Proven track record working with foundries (TSMC, Samsung, etc.) and OSATs (ASE, Amkor, JCET, etc.).
• Willingness to travel up to 25% for onsite supplier engagement, engineering builds, and production ramp support.
• Strong understanding of: Silicon manufacturing processes, including wafer fabrication, dicing, bumping, CoWoS packaging, and testing;
• Proficiency in using ERP systems (e.g., SAP, Oracle) and advanced Excel skills or analytics tools.
• Experience with hardware validation cycles and managing silicon hardware logistics.
• Exceptional program management and organizational skills with the ability to handle complex timelines and interdependencies.
• Effective communicator and cross-functional leader across engineering, validation, and operations teams.

Strong Candidates May Also Have

• Experience working on advanced process nodes (e.g., 5nm, 3nm).
• Familiarity with ATE platforms (Teradyne, Advantest) and test program infrastructure.
• Prior experience managing silicon bring-up in hyperscale computing, AI/ML, or high-performance SoC environments.
• PMP certification or equivalent project/program management training.
• Familiarity with CoWoS or other 2.5D/3D packaging technologies.

Benefits

• Full medical, dental, and vision packages, with generous premium coverage
• Housing subsidy of $2,500/month for those living within walking distance of the office
• Daily lunch and dinner in our office
• Relocation support for those moving to San Jose (Santana Row)

How we’re different

Etched believes in the Bitter Lesson We think most of the progress in the AI field has come from using more FLOPs to train and run models, and the best way to get more FLOPs is to build model-specific hardware. Larger and larger training runs encourage companies to consolidate around fewer model architectures, which creates a market for single-model ASICs.

We are a fully in-person team in San Jose (Santana Row), and greatly value engineering skills. We do not have boundaries between engineering and research, and we expect all of our technical staff to contribute to both as needed.