Synthesis & Static Timing Analysis (STA) Engineer
- Location
- Palo Alto, CA · On-site
- Job type
- Full-time
- Level
- Senior
- Experience
- 5+ years
- Listed
- 21 days ago
Skills & highlights for this role
- Design Compiler
- PrimeTime
- static timing analysis
- SDC constraints
- logic equivalence checking
- Tcl
- Python
Also useful
- Fusion Compiler
- Genus
- Tempus
- Formality
- Conformal
- ECO flows
About this Role
You'll own the path from RTL to a timing-clean netlist. You'll close timing on real silicon programs with leading semiconductor companies while helping Voltai's AI learn to write constraints, diagnose violations, and close timing.
What You’ll Do
- Own logic synthesis and constraint development (SDC) for blocks and full chips.
- Drive timing closure across corners and modes, working with RTL and physical design teams.
- Run and sign off STA, including on-chip variation, crosstalk, and multi-corner multi-mode analysis.
- Perform logic equivalence checking between RTL and netlist.
- Build automation that makes synthesis and timing flows faster and more reliable.
- Evaluate AI-generated constraints and timing fixes, and help define what good looks like.
What We’re Looking For
- 5+ years of synthesis and STA experience on production tapeouts.
- Deep experience with Design Compiler/Fusion Compiler or Genus, and PrimeTime or Tempus.
- Strong SDC skills: clocks, exceptions, generated clocks, and multi-mode constraints.
- Experience with logic equivalence checking (Formality or Conformal).
- Strong Tcl and Python scripting.
Bonus Points
- Advanced node experience (7nm and below).
- Experience with ECO flows and timing signoff methodology.
- Interest in AI-assisted design tools.
About Voltai
Voltai is developing world models, and agents to learn, evaluate, plan, experiment, and interact with the physical world. We are starting out with understanding and building hardware; electronics systems and semiconductors where AI can design and create beyond human cognitive limits.
About the Team
Backed by Silicon Valley’s top investors, Stanford University, and CEOs/Presidents of Google, AMD, Broadcom, Marvell, etc. We are a team of previous Stanford professors, SAIL researchers, Olympiad medalists (IPhO, IOI, etc.), the inventors of IC3 and the Murphi verification system, CTOs of Synopsys & GlobalFoundries, Head of Sales & CRO of Cadence, former US Secretary of Defense, National Security Advisor, and Senior Foreign-Policy Advisor to four US presidents.
From Voltai's careers page, first listed on Rolev.ai on October 19, 2026. Rolev.ai is not the employer.
How Rolev.ai helps with this application
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Common questions
Where is the Synthesis & Static Timing Analysis (STA) Engineer job at Voltai located?
This Synthesis & Static Timing Analysis (STA) Engineer position at Voltai is located in Palo Alto, CA (On-site). Always check Voltai's application page for specific state eligibility or relocation policies.
What qualifications are required for Synthesis & Static Timing Analysis (STA) Engineer at Voltai?
For the Synthesis & Static Timing Analysis (STA) Engineer role, Voltai highlights 5+ years of relevant experience; experience with Design Compiler, PrimeTime, static timing analysis, SDC constraints, logic equivalence checking, Tcl. Rolev.ai can score your existing resume against these requirements and show any skill gaps before you apply.
How do I apply for the Synthesis & Static Timing Analysis (STA) Engineer position at Voltai?
This listing links directly to Voltai's Ashby application page. You can apply directly on Voltai's site, or use Rolev.ai to check your resume fit, generate a zero-hallucination tailored resume and cover letter for this posting, and autofill the Ashby application form in 1 click with the Rolev.ai Chrome extension. You always review the form and press Submit yourself.