Design Verification Engineer
- Location
- Sunnyvale · On-site
- Job type
- Full-time
- Level
- Senior
- Education
- Bachelor's degree
- Listed
- 13 days ago
Skills & highlights for this role
- C programming
- C++
- Assembly programming
- Verilog
- SystemVerilog
- Makefile
- C compilation flow
- Constrained random testing
- Debugging
- Reusable verification frameworks
- Digital logic design
- Chip architecture
- Microarchitecture
- Test plan development
Also useful
- UVM
- Industry standard interfaces
- ARM V7
- ARM V8
- CPU architecture
- Instruction sets
- Embedded C tests in UVM/System TB
- Python scripting
Summary
Would you like to join Apple’s growing wireless silicon development team? Our wireless SOC organization is responsible for all aspects of wireless silicon development with a particular emphasis on highly energy efficient design and new technologies that transform the user experience at the product level, all of which is driven by a world-class vertically integrated engineering team spanning RF/Analog architecture and design, Systems/PHY/MAC architecture and design, VLSI/RTL design and integration, Emulation, Design Verification, Test and Validation, and FW/SW engineering.
About the role
As a Design Verification Engineer, you will be at the center of a chip design effort collaborating with all disciplines, with a critical impact on getting functional products to millions of customers quickly. You will play a key role in designing and implementing C tests for the wireless SoCs verification and power analysis.
Responsibilities
- Work closely with architecture and RTL power designers on defining power vector tests and verifying functionality correctness of the Wireless SoC design
- Develop test plan and test environments in C or UVM
- Develop complex power vector tests for wireless protocol designs in C or assembly
- Preparing and executing the test plan and performing reviews with the cross functional teams
- Collaborating cross functionally with Design, Architecture, Power, Silicon Validation, Performance and SW Teams
Minimum requirement of a bachelors degree
- Experience with C/C++/assembly programming and Verilog/SystemVerilog
- Understand C compilation flow and makefile
- Solid verification skills in problem solving, constrained random testing, and debugging
- Solid understanding of reusable verification framework
- Knowledge of digital logic design, chip architecture, and microarchitecture
- Develop complex tests or power vectors in assembly, or C according to test plans
MSEE preferred
- Knowledge of industry standard interfaces
- Understanding of ARM V7 or V8 architecture
- Experience in setting UVM/System TB with embedded C tests
- Good understanding of CPU architecture and instruction sets
Experience in System level tests with Python or other Scripting language
- Excellent analytical and debug skills
- Experience in UVM DV
- Experience with porting simulation tests to emulation
- Knowledge of wireless protocols
Additional information
Should be a great teammate with excellent communication skills and be able to work independently on the verification efforts
From Apple's careers page, first listed on Rolev.ai on October 27, 2026. Rolev.ai is not the employer.
How Rolev.ai helps with this application
Rolev.ai is a job search and application tool for US job seekers. For this Design Verification Engineer role at Apple, it shows how your resume fits, tailors your resume to the posting, and prepares the application for you to review.
See how you fit
Openings from employer career sites are ranked against your whole resume—and searchable inside Claude, ChatGPT, and Cursor via Rolev.ai MCP.
Tailor without inventing
Every change to your resume is checked against your original. New experience goes in only with your yes—zero fabricated claims.
Draft the full kit
Tailored and Full Match resumes, role-specific cover letters, and answers to employer screening questions are prepared in seconds.
1-Click Extension Autofill
The Chrome extension fills the employer's Greenhouse, Workday, Lever, or Ashby form in 1 click. You review it and press Submit.
Similar roles
More at Apple
All Apple jobsCommon questions
Where is the Design Verification Engineer job at Apple located?
This Design Verification Engineer position at Apple is located in Sunnyvale (On-site). Always check Apple's application page for specific state eligibility or relocation policies.
What qualifications are required for Design Verification Engineer at Apple?
For the Design Verification Engineer role, Apple highlights a bachelor's degree; experience with C programming, C++, Assembly programming, Verilog, SystemVerilog, Makefile. Rolev.ai can score your existing resume against these requirements and show any skill gaps before you apply.
How do I apply for the Design Verification Engineer position at Apple?
This listing links directly to Apple's application page. You can apply directly on Apple's site, or use Rolev.ai to check your resume fit, generate a zero-hallucination tailored resume and cover letter for this posting, and autofill the application form in 1 click with the Rolev.ai Chrome extension. You always review the form and press Submit yourself.