Electronics Engineer Jobs in San Jose, CA - Page 3
Electronics Engineer openings in San Jose, CA from employers' own career sites, newest first. Rolev.ai ranks them against your resume and tailors it to each posting.
- Open positions
- 83
- Median advertised pay
- $205,975 per year
Newest Electronics Engineer openings in San Jose, CA
Principal Engineer, PHY/MAC Design (P)
$216k – $220k/yrInnoPhase IoT · San Jose, CA (On-site) · 30 days ago
If you are keen to work with a bunch of brilliant people with various backgrounds, if you share the same value of working smart and celebrating successes, if you have enthusiasm for big…
- Full-time
- Executive
- 10+ years
- SystemVerilog RTL design
- digital signal processing
- WiFi physical layer
Signal Integrity Engineer Intern
$35 – $55/hrAstera Labs · San Jose, CA (On-site) · 30 days ago
Location: San Jose, California, United States
- Internship
- Entry level
- signal integrity analysis
- S-parameter extraction
- PCB design
Product Applications Engineer NCG (Sco 1)
$140k – $150k/yrAstera Labs · San Jose, CA (On-site) · 30 days ago
As an Astera Labs Product Applications Engineer, you will tackle complex debugging challenges that span from low-level firmware configuration to PCB hardware design and full system-level…
- Full-time
- Entry level
- C firmware
- Python
- PCIe
Design Engineering Intern (CCE2)
$35 – $55/hrAstera Labs · San Jose, CA (On-site) · 30 days ago
Join the CCE2 Design Engineering team and gain hands-on experience developing digital logic for advanced connectivity ASICs.
- Internship
- Entry level
- Verilog
- SystemVerilog
- digital logic design
Digital Design Engineering Intern
$35 – $55/hrAstera Labs · San Jose, CA (On-site) · 30 days ago
Astera Labs is seeking a Digital Design Intern to contribute to the development of ASIC and digital hardware blocks.
- Internship
- Entry level
- Verilog
- SystemVerilog
- RTL design
Emulation Engineering Intern
$35 – $55/hrAstera Labs · San Jose, CA (On-site) · 30 days ago
Astera Labs is seeking an Emulation Engineering Intern to help enable fast, repeatable pre-silicon validation of complex ASIC and system designs.
- Internship
- Entry level
- RTL
- SystemVerilog
- Python
Analog Mixed Signal Engineer Intern
$47 – $70/hrAstera Labs · San Jose, CA (On-site) · 30 days ago
As an Analog/Mixed-Signal IC Design Engineer Intern, you will be part of a key team designing sophisticated advanced node CMOS products.
- Internship
- Entry level
- analog mixed-signal circuit design
- ADC/DAC data converters
- PLL design
Muon Space · San Jose, CA (Hybrid) · 30 days ago
Muon Space is seeking a Senior FPGA Engineer specialized in onboard networking, cryptography and security to design the network fabric and security architecture of our next-generation…
- Full-time
- Senior
- FPGA design
- RTL
- Ethernet PHY/MAC integration
Rivet Industries · San Jose, CA (On-site) · 30 days ago
Due to the nature of our business and compliance with federal regulations, all candidates must be a "U.S. Person". Upon hire, you will be required to provide documentation
- Full-time
- Director
- 4+ years
- MIL-STD-461G
- EMI/EMC testing
- PCB layout review
On/Off-Chip SI/PI Engineer
$150k – $320k/yrSK hynix · San Jose, CA (On-site) · 30 days ago
This role serves as a critical technical liaison between HQ engineering teams and key U.S.-based customers, providing hands-on SI/PI analysis to resolve immed
- Full-time
- Senior
- 3+ years
- signal integrity
- power integrity
- HFSS
Staff Engineer, DRAM Field Application
$140k – $180k/yrSK hynix · San Jose, CA (On-site) · 30 days ago
The DRAM Field Application Engineer will lead customer-facing technical engagements and serve as a senior technical and strategic interface between key customers, contract manufacturers…
- Full-time
- Lead / Staff
- 10+ years
- DRAM architecture
- system-level debugging
- failure analysis
Sr. Principal Product Applications Engineer - Custom Solutions
$205k – $260k/yrAstera Labs · San Jose, CA (On-site) · 30 days ago
Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions.
- Full-time
- Director
- 10+ years
- PCIe
- Ethernet
- SerDes
Tech Lead, Digital Design Engineer
$176k – $195k/yrAstera Labs · San Jose, CA (On-site) · 30 days ago
Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions.
- Full-time
- Lead / Staff
- 5+ years
- RTL design
- synthesis and timing closure
- UVM verification
Tech Lead Engineer, Design Verification
$176k – $195k/yrAstera Labs · San Jose, CA (On-site) · 30 days ago
Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions.
- Full-time
- Lead / Staff
- 5+ years
- SystemVerilog
- UVM
- PCIe
Astera Labs · San Jose, CA (On-site) · 30 days ago
Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions.
- Full-time
- Executive
- 10+ years
- PCIe LTSSM
- silicon bring-up and debug
- high-speed oscilloscopes
Principal Verification Engineer
$185k – $230k/yrAstera Labs · San Jose, CA · 30 days ago
Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions.
- Full-time
- Lead / Staff
- 8+ years
- SystemVerilog
- UVM
- functional coverage analysis
Principal Emulation Engineer
$209k – $230k/yrAstera Labs · San Jose, CA (On-site) · 30 days ago
Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions.
- Full-time
- Lead / Staff
- 8+ years
- SystemVerilog
- PCIe
- emulation
Principal Engineer - Validation Engineering
$185k – $240k/yrAstera Labs · San Jose, CA (On-site) · 30 days ago
Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions.
- Full-time
- Lead / Staff
- 8+ years
- PCIe
- CXL
- Ethernet
Principal Emulation Engineer
$207k – $230k/yrAstera Labs · San Jose, CA (On-site) · 30 days ago
Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions.
- Full-time
- Lead / Staff
- 8+ years
- SystemVerilog
- PCI Express
- Python
Principal Physical Design Engineer, STA
$209k – $250k/yrAstera Labs · San Jose, CA (On-site) · 30 days ago
Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions.
- Full-time
- Director
- 10+ years
- static timing analysis (STA)
- SDC constraints
- TSMC 7nm sign-off
How Rolev.ai helps with Electronics Engineer jobs
Rolev.ai is a job search and application tool for US job seekers. It shows which Electronics Engineer jobs in San Jose, CA fit your resume, tailors your resume to each posting, and prepares the application for you to review.
See how you fit
Openings from employer career sites are ranked against your whole resume—and searchable inside Claude, ChatGPT, and Cursor via Rolev.ai MCP.
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Draft the full kit
Tailored and Full Match resumes, role-specific cover letters, and answers to employer screening questions are prepared in seconds.
1-Click Extension Autofill
The Chrome extension fills the employer's Greenhouse, Workday, Lever, or Ashby form in 1 click. You review it and press Submit.
Common questions
How much does a Electronics Engineer make in San Jose, CA?
Based on 44 Electronics Engineer postings in San Jose, CA that state pay, the median advertised salary is $205,975 per year. Individual offers vary with experience, employer and location.
Does Rolev.ai apply to these jobs for me?
No. Rolev.ai tailors your resume and the Chrome extension fills the employer's form, and you review it and press Submit yourself.
Where do these listings come from?
From employers' public career sites. Each listing links to the employer's own application page.