Electronics Engineer Jobs in San Jose, CA - Page 4
Electronics Engineer openings in San Jose, CA from employers' own career sites, newest first. Rolev.ai ranks them against your resume and tailors it to each posting.
- Open positions
- 83
- Median advertised pay
- $205,975 per year
Newest Electronics Engineer openings in San Jose, CA
Senior Director System Validation Engineer
$240k – $300k/yrAstera Labs · San Jose, CA (On-site) · 30 days ago
Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions.
- Full-time
- Director
- 15+ years
- SoC validation
- silicon bring-up
- post-silicon debug
Principal Silicon Validation Engineer
$205k – $260k/yrAstera Labs · San Jose, CA (On-site) · 30 days ago
Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions.
- Full-time
- Lead / Staff
- 10+ years
- PCIe
- 802.3 Ethernet
- BERT and oscilloscope lab testing
Principal Product Application Engineer - PCIe
$171k – $220k/yrAstera Labs · San Jose, CA (On-site) · 30 days ago
Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions.
- Full-time
- Lead / Staff
- 8+ years
- PCIe Gen4/Gen5/Gen6
- oscilloscopes
- protocol analyzers
Principal Product Technical Leader - AEC/SCM
$160k – $200k/yrAstera Labs · San Jose, CA (On-site) · 30 days ago
Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions.
- Full-time
- Lead / Staff
- high-speed signal integrity
- PCB design
- electrical compliance testing
Principal Digital Design Engineer (AI Fabric)
$185k – $230k/yrAstera Labs · San Jose, CA (On-site) · 30 days ago
Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions.
- Full-time
- Lead / Staff
- 8+ years
- RTL coding
- timing closure
- DFT implementation
Design Verification Tech Lead- SerDes/PHY IP
$160k – $200k/yrAstera Labs · San Jose, CA (On-site) · 30 days ago
Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions.
- Full-time
- Executive
- 5+ years
- SystemVerilog
- UVM
- PHY design verification
Principal SerDes Bring-up Validation Engineer
$185k – $240k/yrAstera Labs · San Jose, CA (On-site) · 30 days ago
Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions.
- Full-time
- Lead / Staff
- 8+ years
- SerDes bring-up
- post-silicon validation
- PAM4 signaling
Etched · San Jose, CA (On-site) · 30 days ago
We are seeking a highly skilled and motivated Design For Testability (DFT) Engineer to join our dynamic team.
- Full-time
- Director
- 10+ years
- System Verilog
- Synopsys DFT Compiler
- Mentor Tessent
Etched · San Jose, CA (On-site) · 30 days ago
We are seeking a skilled and motivated Silicon Validation Firmware Engineer to develop the firmware and low-level software that validates our AI/ML accelerator ASICs across their entire…
- Full-time
- Mid-level
- C/C++
- Python
- SoC architecture
RTL Design Engineer
On-siteEtched · San Jose, CA (On-site) · 30 days ago
As an RTL Engineer at Etched, you will be critical in ensuring that our AI chips operate correctly and efficiently.
- Full-time
- Mid-level
- 5+ years
- RTL design
- high-speed digital logic
- Verilog synthesis
Emulation Engineer, Hardware Prototyping (HAPS)
$150k – $275k/yrEtched · San Jose, CA (On-site) · 30 days ago
Own HAPS bring-up.
- Full-time
- Mid-level
- FPGA prototyping
- SystemVerilog
- Verilog
Hardware Validation Engineer
On-siteEtched · San Jose, CA (On-site) · 30 days ago
We are seeking an experienced and motivated Hardware Validation Engineer to validate system hardware and printed circuit board (PCB) functionality and ensure robust power and signal…
- Full-time
- Mid-level
- PCB-level debugging
- power and signal integrity measurement
- PCIe
Etched · San Jose, CA (On-site) · 30 days ago
We are seeking a highly skilled and motivated Post Silicon Validation Engineer to join our dynamic team.
- Full-time
- Mid-level
- 7+ years
- post-silicon validation
- ASIC bring-up and debug
- C
Etched · San Jose, CA (On-site) · 30 days ago
Etched is building a new category of AI hardware: frontier inference clusters.
- Full-time
- Lead / Staff
- 5+ years
- physical design
- RTL-to-GDSII
- timing closure
NAND Array Engineer
$140k – $255k/yrSolidigm · San Jose, CA (Hybrid) · 30 days ago
Solidigm is looking for a highly motivated and technically skilled NAND Array Engineer to join our Performance and Reliability Team.
- Full-time
- Senior
- 3+ years
- NAND device physics
- statistical analysis
- Python
Samsung · San Jose, CA (On-site) · 30 days ago
To provide the best candidate experience amidst our high application volumes, each candidate is limited to 10 applications across all open jobs within a 6-month period.
- Full-time
- Senior
- 5+ years
- RTL design
- microarchitecture
- memory controller design
Samsung · San Jose, CA (On-site) · 30 days ago
To provide the best candidate experience amidst our high application volumes, each candidate is limited to 10 applications across all open jobs within a 6-month period.
- Full-time
- Lead / Staff
- 8+ years
- PCIe protocol
- LTSSM and link training
- C/C++ embedded firmware
Samsung · San Jose, CA (On-site) · 30 days ago
To provide the best candidate experience amidst our high application volumes, each candidate is limited to 10 applications across all open jobs within a 6-month period.
- Full-time
- Lead / Staff
- 15+ years
- UVM
- SystemVerilog
- C/C++
Samsung · San Jose, CA (On-site) · 30 days ago
Samsung Semiconductor, Inc. is looking for a DRAM application engineer to join our application engineering (AE) team in San Jose, CA.
- Full-time
- Senior
- 3+ years
- DRAM
- signal integrity/power integrity
- oscilloscope
How Rolev.ai helps with Electronics Engineer jobs
Rolev.ai is a job search and application tool for US job seekers. It shows which Electronics Engineer jobs in San Jose, CA fit your resume, tailors your resume to each posting, and prepares the application for you to review.
See how you fit
Openings from employer career sites are ranked against your whole resume—and searchable inside Claude, ChatGPT, and Cursor via Rolev.ai MCP.
Tailor without inventing
Every change to your resume is checked against your original. New experience goes in only with your yes—zero fabricated claims.
Draft the full kit
Tailored and Full Match resumes, role-specific cover letters, and answers to employer screening questions are prepared in seconds.
1-Click Extension Autofill
The Chrome extension fills the employer's Greenhouse, Workday, Lever, or Ashby form in 1 click. You review it and press Submit.
Common questions
How much does a Electronics Engineer make in San Jose, CA?
Based on 44 Electronics Engineer postings in San Jose, CA that state pay, the median advertised salary is $205,975 per year. Individual offers vary with experience, employer and location.
Does Rolev.ai apply to these jobs for me?
No. Rolev.ai tailors your resume and the Chrome extension fills the employer's form, and you review it and press Submit yourself.
Where do these listings come from?
From employers' public career sites. Each listing links to the employer's own application page.